The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a low-dielectric interlayer insulation film suitable for high-speed operation, and a fabrication process thereof.
In a semiconductor integrated circuit in which a number of active device elements, such as MOS transistors, are integrated on a common substrate, it is practiced to provide a multilayer interconnection structure for electrically interconnecting these active device elements. In a multilayer interconnection structure, a first-layer interconnection pattern is covered by a first-layer interlayer insulation film, and a second-layer interconnection pattern is provided on such a first-layer interlayer insulation film. Further, a second-layer interlayer insulation film covers the second-layer interconnection pattern thus formed on the first-layer interlayer insulation film. Further, there may be a third-layer interconnection pattern and a third-layer interlayer insulation film on the second-layer interlayer insulation film.
When such a multilayer interconnection structure is to be formed in a high-speed semiconductor integrated circuit such as a logic integrated circuit or a high-speed memory integrated circuit, it is desirable to reduce the dielectric constant of the insulation film constituting the interlayer insulation film as low as possible. This demand is particularly acute in the ultrafine semiconductor integrated circuits fabricated according to the design rule of 0.3 .mu.m or stricter. It should be noted that such ultrafine semiconductor integrated circuits generally use four or more layers for the multilayer interconnection structure and the total length of the interconnection patterns therein inevitably becomes a very large value.
When a conventional insulation film such as SiO.sub.2, which is formed by a parallel-plate plasma CVD process or by a high-temperature CVD process, or an SOG film which is formed by a spin-coating process, is to be used for the interlayer insulation film in such a multilayer interconnection structure, there arises a problem of increase in the impedance as a result of the electrostatic inductance between the interconnection patterns. It should be noted that such an increase in the impedance leads to the problems of response delay or increase of electrical power consumption.
In view of the shortcomings of the conventional interlayer insulation films, there has been a proposal to deposit a F-doped, low-dielectric SiO.sub.2 film by a high-density plasma CVD process. The F-doped SiO.sub.2 film thus deposited may be subjected to a chemical mechanical polishing (CMP) process for planarization. In fact, it is possible to reduce the dielectric constant of the interlayer insulation film to 3.4-3.5 by adding F (fluorine) to the SiO.sub.2 interlayer insulation film.
FIGS. 1A and 1B show typical examples of conventional multilayer interconnection structure.
Referring to FIG. 1A showing an example multilayer interconnection structure 10A, it can be seen that the multilayer interconnection structure 10A is formed on a substrate 1 in which active device elements such as transistors are formed. The substrate 1 further includes an interlayer insulation film covering the foregoing active devices.
On the substrate 1, there is formed an interconnection pattern 2 of Al or an Al-alloy, and an SiO.sub.2 film 3 is formed on the substrate 1 typically by a plasma CVD process so as to cover the interconnection pattern 2 in conformity with the shape thereof. Further, there is formed a planarization film 4 typically of SOG, such that the planarization film 4 covers the SiO.sub.2 film 3 with a planarized top surface, and an SiO.sub.2 film 5 is formed on the planarization film 4 by a plasma CVD process.
In the example of FIG. 1B showing a multilayer interconnection structure 10B, on the other hand, the interconnection pattern 2 on the substrate 1 is covered by a planarized interlayer insulation film 6 of SiO.sub.2 formed by a high-density plasma CVD process, wherein the planarized interlayer insulation film 6 has a planarized top surface. Further, the planarized interlayer insulation film 6 is covered by an SiO.sub.2 film 7 formed by a plasma CVD process.
In any of the multilayer interconnection structures 10A and 10B of FIGS. 1A and 1B, the SiO.sub.2 film 5 or the SiO.sub.2 film 7 is covered by a passivation film of SiN.
In any of the conventional multilayer interconnection structures, the SiO.sub.2 film 3, 4 or 6 generally has a dielectric constant of 4.1 or more. Thus, due to the effect of the stray capacitance, the problem of signal transmission delay appears conspicuously when the SiO.sub.2 film 3, 4 or 6 is used for the interlayer insulation film of ultra-fine semiconductor devices that are fabricated according to the submicron rules. Further, there arises a difficulty in increasing the clock speed in such ultra-fine semiconductor devices that uses the interlayer insulation film having a dielectric constant of 4.1 or more.
As noted already, it is possible to reduce the dielectric constant of the interlayer insulation film 3, 4 or 6 to the value of 3.4-3.5 by using SiO.sub.2 added with F. By using such a F-doped SiO.sub.2 film for the interlayer insulation film, it becomes possible to increase the operational speed of the ultra-fine semiconductor devices. However, such a F-doped SiO.sub.2 film has a drawback in that the adhesion of the SiO.sub.2 film to the interconnection pattern is insufficient and that the F-doped SiO.sub.2 film thus formed tends to cause an exfoliation.